Path-Based Statistical Timing Analysis Considering Inter- and Intra-Die Correlations

TLDR

Process variation has become a significant concern for static timing analysis. The paper proposes a new method for path‑based statistical timing analysis. The method models inter‑ and intra‑die device length variations, enumerates inter‑die variations, analytically treats intra‑die variations, and incorporates spatial correlation to compute path delay probability distributions efficiently. Experiments on an industrial microprocessor show that the proposed approach accurately predicts path delay distributions, outperforming traditional analysis and matching Monte‑Carlo simulation results.

Abstract

Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability distribution using a combination of device length enumeration for inter-die variation and an analytical approach for intradie variation. We also propose a simple and effective model of spatial correlation of intra-die device length variation. The analysis is then extended to include spatial correlation. We test the proposed methods on paths from an industrial high-performance microprocessor and present comparisons with traditional path analysis which does not distinguish between inter- and intra-die variations. The characteristics of the device length distributions were obtained from measured data of 8 test chips with a total of 17688 device length measurements. Spatial correlation data was also obtained from these measurements. We demonstrate the accuracy of the proposed approach by comparing our results with Monte-Carlo simulation.