Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh

Abstract

NoC architectures can be adopted to support general communications among multiple IPs over multi-processor systems on chip (SoCs). In this work we illustrate the modeling and simulation-based analysis of some recent architectures for network on chip (NoC). Specifically, the ring, spidergon and 2D mesh NoC topologies have been compared, both under uniform load and under more realistic load assumptions in the SoC domain. The main performance indexes considered are NoC throughput and latency, as a function of variable data-injection rates, source and destination distributions, and variable number of nodes. Results show that the spidergon topology is a good trade-off between performance, scalability of the most efficient architectures inherited from the parallel computing systems design, constraints about simple management, and small energy and area requirements for SoCs