A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise

Abstract

Techniques are proposed to dramatically reduce the impact of quantization noise in /spl Sigma//spl Delta/ fractional-N synthesizers, thereby improving the existing tradeoff between phase noise and bandwidth that exists in these systems. The key innovation is the introduction of new techniques to overcome nonidealities in a phase-frequency detector (PFD)/digital-to-analog converter (DAC) structure, which combines the functionality of both phase detector and cancellation DAC into a single element. The proposed architecture achieves better gain matching between the phase-error signal and cancellation DAC than offered by previous approaches. Dynamic element matching techniques are introduced to mitigate the effects of PFD/DAC unit element and timing mismatch on synthesizer phase noise performance. We present behavioral simulations of an example application of this technique that demonstrates 36 dB reduction in broad-band quantization-induced phase noise with the use of a 7-b PFD/DAC. Simulations further demonstrate that fractional spurs are rejected to levels <-90 dBc when a low-cost, low-overhead digital gain correction technique is employed.