The Operation Algorithm for Improving the Reliability of TLC (Triple Level Cell) NAND Flash Characteristics

Abstract

As the NAND flash market demand for larger capacity with low cost increases, the feature-size scaling and multi-level per bit have been developed. In this paper, we present the newly adopted operation algorithms and their results such as intelligent ISPE(Incremental Step Pulse Erase), various biasing in grouped W/Ls and VNR(Virtual Negative Read) in TLC(Triple Level Cell) NAND flash.