Scaling $LC$ Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Abstract

We present an oscillator design method that reduces the area of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> oscillators in extremely scaled CMOS technologies by taking advantage of the high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> of the transistors. The oscillator is scaled to operate at a higher frequency and is followed by a fixed-ratio divider. It maintains the same power consumption and performance for a given wanted output frequency while occupying a much smaller area. In principle, by scaling up the oscillation frequency <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> times, a factor of 1/ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> can be obtained in inductor area reduction. Simulated results show that with uniformly scaled inductors, the figure of merit (FoM) of the scaled oscillators at 1, 2, 4, and 8 GHz can be within a 1-dB difference, whereas the figure of merit normalized for area (FoMA) improves with the oscillation frequency.