Placement-based partitioning for lookup-table-based FPGAs

Abstract

Lookup-table-based field-programmable gate array (FPGA) logic blocks contain multiple lookup-tables, flip flops, and other features. The partitioning of this logic into physical blocks has a logical component, traditionally handled as part of technology mapping in logic synthesis, and a physical component, traditionally handled by placement in physical design. However, methods that use a purely logical partitioning give designs that are difficult to route, and methods that use a purely physical partitioning do not result in legal logical blocks. The authors describe a partitioning method that includes both logic-based and placement-based steps to achieve a high-quality legal partitioning. The method simultaneously generates an initial placement for the design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>