Short-channel MOSFETs in the punchthrough current mode

Abstract

Results of two-dimensional device analysis are compared with experiment for 0.8-/spl mu/m Si-gate ion-implanted MOS devices operated under conditions of punchthrough transport. Characterization of the punchthrough mode of device operation with experiment and simulation has shown that the observed power-law dependence is related to the drain-induced barrier-height lowering. Results of the simulation show the dependence of the punchthrough current upon the range and maximum doping level of the channel implantation. Increasing the substrate-bias or applying a negative-gate voltage is shown to increase the punchthrough voltage. This simulation, which combines results of the process-simulation program and device-simulation program, is shown to predict the behavior of this mode of operation where previous one-dimensional theory has failed.