Localized thermal effect of sub-16nm FinFET technologies and its impact on circuit reliability designs and methodologies

Abstract

Localized Thermal Effect (LTE, i.e. self-heating) is one of the greatest reliability concerns of FinFET technologies. This paper introduced some new reliability design methodologies for aging and electromigration to address the LTE effects at circuit level. An industry level PLL circuit designed on a leading foundry's sub-16nm FinFET process was applied with the new methodologies to analyze the LTE impacts on the circuit reliability. The results not only showed very different behaviors and impacts of temperature accelerated degradations on circuit performance and functionality with and without comprehending LTE effects, but also demonstrated the effectiveness of the new LTE-aware design for reliability methodologies developed and deployed at Hisilicon.