LDD design tradeoffs for single transistor latch-up and hot carrier degradation control in accumulation mode FD SOI MOSFET's

Abstract

An experimental study has been conducted of the design tradeoffs of fully-depleted (FD) accumulation mode Silicon-on-Insulator (SOI) MOSFET's with regard to hot carrier reliability, single transistor latch-up and device performance. Three drain designs were considered, using Large-Tilt-Angle Implantation (LATID) for the LDD formation. Structures incorporating 0/spl deg/ angle LDD implant, large angle LDD implant, and no LDD were fabricated, and their hot carrier reliability, single transistor latch-up voltage, and device performance in terms of drive current and speed were determined. Correct interpretation of the experimental results was aided by performing PISCES numerical simulations. It was found that the structure with the best hot carrier reliability (large angle LDD implant) has the worst case latch-up voltage, and the one with the worst hot carrier reliability (no LDD implant) has the best latch-up voltage. Overall good device performance with acceptable hot carrier reliability and latch-up voltage is obtained with the 0/spl deg/ angle LDD implant.