AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) · 2003 · 16 citations · 4 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyLow-noise Circuit DesignMixed-signal Integrated Circuit DesignNoise In Analog CircuitsTransistor BiasingBias Circuit DesignBiasing TechniquesComplementary Metal-oxide-semiconductor BiasingLow-power Amplifier DesignOverhead ReductionSelf-biasingSupply Voltage OptimizationTransconductor Design
This paper describes a 1.8 V self-biased complementary folded cascode(SB-CFC) amplifier. We propose a new self biasing scheme for the folded cascode amplifier which eliminates 6 external bias voltages and related biasing circuits. The required minimum power supply voltage is reduced to 1.8 V and the output voltage swings are increased. With our new self-biasing scheme the area and power overhead, susceptibility of the bias lines to noise and crosstalk, and design time are reduced.
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