Memory bank and register allocation in software synthesis for ASIPs

Abstract

Abstract—An architectural feature commonly found in digital signal processors (DSPs) is multiple data-memory banks. This fea-ture increases memory bandwidth by permitting multiple memory accesses to occur in parallel when the referenced variables belong to different memory banks and the registers involved are allocated according to a strict set of conditions. Unfortunately, current com-piler technology is unable to take advantage of the potential in-crease in parallelism offered by such architectures. Consequently, most application software for DSP systems is hand-written – a very time-consuming task. We present an algorithm which attempts to maximize the ben-efit of this architectural feature. While previous approaches have decoupled the phases of register allocation and memory bank as-signment, our algorithm performs these two phases simultaneously. Experimental results demonstrate that our algorithm substantially improves the code quality of many compiler-generated and even hand-written programs. I.