Comparison of gate-induced drain leakage and charge pumping measurements for determining lateral interface trap profiles in electrically stressed MOSFETs

Abstract

Improved methods for extracting lateral spatial profiles of interface traps in electrically stressed MOSFETs from gate-induced drain leakage and charge pumping measurements are proposed. Simplified theoretical models are developed. The formal similarity of the two methods is shown. The results obtained on submicron MOSFET after uniform (Fowler-Nordheim) and nonuniform (hot carrier) stress are compared and found to be in good agreement. The relative merits of these techniques are discussed.