Two-resistor compact modeling for multiple die and multi-chip packages

Abstract

Compact thermal models have been extremely valuable in the quick and simple analysis of electronic packages because of their simplicity in implementation and minimal computational resource requirement. The recent trends in the market resulted in an increasingly high level of complexity in electronic package design and thus the need for a simplistic approach to routine analysis. The key challenge has always been the derivation of highly accurate compact models. This paper presents detailed analysis of the two-resistance compact models for prediction of the thermal performance of stacked-die chip-scale packages. The compact models are compared to the detailed model under different boundary condition scenarios: still air environment (JESD51-2), ring cold plate test (JESD51-8), the top cold plate test, and a cell phone mock-up environment. Results of the analyses show good correlation between the two-resistance models and the detailed multi-die stacked packages considered. A representative four-resistance model for a two-package stack technology has been demonstrated to provide accurate results in different environments.