Ultralow-Loss and Broadband Micromachined Transmission Line Inductors for 30–60 GHz CMOS RFIC Applications

Abstract

In this paper, for the first time, we demonstrate that ultralow-loss and broadband transmission line (TL) inductors can be obtained by using the CMOS-process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the TL inductors. The results show that a 112.8% (from 14.37 to 30.58) and a 201.1% (from 6.33 to 19.06) increase in Q-factor, a 9.7% (from 0.91 to 0.998) and a 28.3% (from 0.778 to 0.998) increase in maximum available power gain G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> , and a 0.404-dB (from 0.412 to 7.6times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> dB) and a 1.082-dB (from 1.09 to 8.4times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> dB) reduction in minimum noise figure NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> were achieved at 30 and 60 GHz, respectively, for a 162.2 pH TL inductor after the backside ICP dry etching. The state-of-the-art performances of the on-chip TL inductors-on-air suggest that they are very suitable for application to realize ultralow-noise 30-60-GHz CMOS radio-frequency integrated circuit. In addition, the CMOS-process compatible backside ICP etching technique is very promising for system-on-a-chip applications.