A 40-Gb/s Decision Circuit in 90-nm CMOS

Abstract

A low-power 40-Gb/s decision circuit for fiber-optic and mm-wave analog-to-digital converter applications was implemented in two 90-nm processes from two different foundries. The circuit uses a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. It combines low and high-VT MOSFETs to allow for operation from a 1.2-V supply, without compromising speed. Full-rate retiming with jitter reduction and 7 ps rise/fall times is demonstrated at 37 Gb/s and 40 Gb/s from 1.2 V and 1.5 V, respectively. The entire decision circuit dissipates 130 mW from 1.2 V, with a record low power consumption of 10.8 mW per latch.