High-density quaternary logic array chip for knowledge information processing systems

Abstract

A high-density NMOS logic array chip based on quaternary logic implemented for high-speed parallel pattern matching in a knowledge information processing system is described. The logic array can be exploited in real-time applications when the rules are fixed. Based on the appropriate quaternary coding for the contents of working memory and production memory, a double-pattern-matching algorithm for achieving a high-density chip is proposed. One of four states for 2-bit information concerning two elements of a rule is stored in a pattern-matching cell by multiple ion implants, so that the pattern-matching cell is implemented using only a single transistor. It is shown that the chip area for pattern matching is reduced by 30% compared with the corresponding binary logic array.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>