A technique for high ratio LZW compression [logic test vector compression]

Abstract

Reduction of both the test suite size and the download time of test vectors is important in today's system-on-a-chip designs. In this paper, a method for compressing the scan test patterns using the LZW algorithm is presented. This method leverages the large number of "don't-cares" in test vectors in order to improve the compression ratio significantly. The hardware decompression architecture presented here uses existing on-chip embedded memories. Tests using the ISCAS89 and the ITC99 benchmarks show that this method achieves high compression ratios.