Scheduling for IC sort and test with preemptiveness via Lagrangian relaxation

Abstract

This paper presents a Lagrangian relaxation approach for the scheduling problem of an IC sort and test facility. In an integrated circuit (IC) manufacturing environment, a combination of tester, prober, and some hardware facilities is needed for wafer sort while a combination of tester, handler, and some other hardware facilities is needed for final test. To schedule both sorting and testing at the same time, the resource constraints on testers, probers, handlers and hardware have to be dealt with. This paper also extends the Lagrangian relaxation technique to solve a class of preemptive scheduling problems which particularly exist in an IC test floor environment. Numerical examples are given to illustrate the potential of the authors' approach. Comparisons of the authors' results with those obtained by some heuristic rules are also given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>