Application of Symbolic and Bounded Model Checking to the Verification of Logic Control Systems

Abstract

The developer of logic control systems is faced with increasing complexity of the functions to be implemented and, at the same time, increasing demands on the reliability of the resulting software. To analyze the reliability of such complex systems formal methods can be applied. One area of the corresponding research is focused on the application of model checking techniques to Programmable Logic Controllers (PLCs). In this paper a new method to formalize PLC programs together with a model of the cyclic behavior of the PLC is presented. The control systems behavior is modeled, and then the program, written in Instruction List, is formalized and integrated into the model. The formalization in SMV language is suitable for verification using BDD and SAT techniques. Both techniques are compared using first results of a case study.