Interconnect IP node for future system-on-chip designs

TLDR

The architecture targets communication in future gigatransistor SoC designs. The paper introduces an interconnect IP node architecture for flexible on‑chip communication. The node is a packet‑based, parameterized component built from reusable blocks such as FIFOs and routing controllers, serving as a testing platform for evaluating network topologies and routing schemes.

Abstract

An interconnect IP (intellectual Property) node architecture for flexible on-chip communication is introduced. This architecture is targeted for communication in future gigatransistor SoC (System-on-Chip) designs. The interconnect IP will be used as a testing platform when the efficiency of network topologies and routing schemes are investigated for the on-chip environment. The interconnect node uses packet based communication and forms a reusable component itself. The node is constructed from a collection of parameterized and reusable hardware blocks, which include components such as FIFO buffers, routing controllers and standardized interface wrappers. A node can be tuned to fulfill the desired characteristics of communication by selecting the internal architecture properly.