IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003 · 96 citations · 20 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureField-programmable Gate ArraysMicroelectronicsDevice ModelingFpga ArchitectureIntegrated Circuit DesignInterconnect ArchitectureInterconnect DesignInterconnect TechnologyAnalytical ModelsField-programmable Gate Arrays (Fpgas)Interconnect DelayInterconnect Delay AnalysisInterconnect Delay ModelingInterconnect Power DissipationSystem-level ModelingThree-dimensional Integration
In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.
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Jeffrey A. Davis, Vivek De, J.D. Meindl · IEEE Transactions on Electron Devices · 1998 · 240 citations
Engineering, Computer Engineering, Electrical Engineering +17