2009 · 22 citations · 9 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureCryptographyHardware SecurityCryptographic AlgorithmsCryptographic ArchitectureCryptographic ImplementationData EncryptionField-programmable Gate Array ArchitectureSymmetric-key CryptographyAdvanced Encryption StandardArithmetic Of Finite FieldsCombinational Logic DesignCryptographic Accelerator DesignEncryptionEncryption AlgorithmsFinite Field ArithmeticS-box Design
In this paper, improved architectures are proposed for implementation of S-Box and inverse S-Box needed in the Advanced encryption standard (AES) algorithm. These use combinational logic only for implementing SubByte (S-box) and InvSubByte (Inverse S-box). The composite field arithmetic used for implementing S-Box in lower-order Galois field (GF) investigated by several authors recently is used as the basis for deriving the proposed architectures. The resulting hardware requirements as well computation time are presented for the proposed designs and compared with previous work.
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