A compact AES core with on-line error-detection for FPGA applications with modest hardware resources

High-speed VLSI architectures for the AES algorithm

Xinmiao Zhang, Keshab K. Parhi · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2004 · 443 citations

Engineering, Computer Engineering, Computer Science +17

Error analysis and detection procedures for a hardware implementation of the advanced encryption standard

Guido Bertoni, Luca Breveglieri, Israel Koren et al. · IEEE Transactions on Computers · 2003 · 338 citations

Engineering, Computer Engineering, Computer Science +17

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA

A. Hodjat, Ingrid Verbauwhede · 2004 · 219 citations

Engineering, Computer Engineering, Computer Science +17

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers

Ramesh Karri, Kaijie Wu, Pooja Mishra et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2002 · 178 citations

Computing, Computer Engineering, Computer Science +17

Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Gaël Rouvroy, François‐Xavier Standaert, J.-J. Quisquater et al. · 2004 · 159 citations · Full text

Engineering, Computer Engineering, Computer Science +16