A fully operational 1 kb variable threshold Josephson RAM

Abstract

The first fully operational Josephson RAM in LSI level integration is described. The chip is designed as a 4 b* 256-word data RAM unit for a 4 b Josephson computer. A variable-threshold memory cell and the related memory architecture are used. They are so simple in structure that the fabrication can be accomplished using current Josephson junction technology. A directly coupled driver gate for a resistive bit line applies an accurate and stable driving current to the memory cell array. The RAM chip is fabricated with a 3 mu m Nb/Al-oxide/Nb junction technology. For obtaining reliable RAM chips, a plasma-enhanced CVD (chemical-vapor-deposited) silicon dioxide layer is introduced for insulation between the ground plane and the base electrode. The thermal uniformity of the wafer is improved during the oxidation process for making a tunnel barrier. Installing this RAM chip together with a Josephson processor permitted the functions of a computer, including a memory access, to be successfully demonstrated. The access time was found to be 500-520 ps by measuring a test chip.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>