IEEE Journal of Solid-State Circuits · 2013 · 93 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesChip PackagingCmos Circuit DesignIntegrated Circuit DesignInterconnect DesignInterconnect TechnologyLow-power Digital Circuit DesignCharge Pump CircuitsHigh-density InterconnectsHigh-speed InterconnectsLow-power Interconnect DesignOrganic SubstratesSignalingSiliconSingle-ended Signaling
High-speed signaling over high density interconnect on organic package substrates or silicon interposers offers an attractive solution to the off-chip bandwidth limitation problem faced in modern digital systems. In this paper, we describe a signaling system co-designed with the interconnect to take advantage of the characteristics of this environment to enable a high-speed, low area, and low-power die to die link. Ground-Referenced Signaling (GRS) is a single-ended signaling system that eliminates the major problems traditionally associated with single-ended design by using the ground plane as the reference and signaling above and below ground. This design employs a novel charge pump driver that additionally eliminates the issue of simultaneous switching noise with data independent current consumption. Silicon measurements from a test chip implementing two 16-lane links, with forwarded clocks, in a standard 28 nm process demonstrate 20 Gb/s operation at 0.54 pJ/bit over 4.5 mm organic substrate channels at a nominal 0.9 V power supply voltage. Timing margins at the receiver are <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${>}$</tex></formula> 0.3 UI at a BER of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${<}$</tex> </formula> 10 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{-12}$</tex> </formula> . We estimate BER <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${<}$</tex> </formula> 10 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{-25}$</tex> </formula> at the eye center.
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Wm. A. Wulf, Sally A. McKee · ACM SIGARCH Computer Architecture News · 1995 · 1.5K citations
Hitting the Memory Wall: Implications of the Obvious
Wm. A. Wulf, Sally A. McKee · 1995 · 1.4K citations
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
John W. Poulton, R. Palmer, Andrew M. Fuller et al. · IEEE Journal of Solid-State Circuits · 2007 · 240 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 27-mW 3.6-Gb/s I/O Transceiver
K.-L.J. Wong, Hamid Hatamkhani, Mozhgan Mansuri et al. · IEEE Journal of Solid-State Circuits · 2004 · 121 citations
Engineering, Computer Engineering, Electrical Engineering +17