A 13.3-Mb/s 0.35-μm CMOS analog turbo decoder IC with a configurable interleaver

Abstract

Circuits and an IC implementation of a four-state, block length 16, three-metal one-poly 0.35-μm CMOS analog turbo decoder with a fully programmable interleaver are presented. The IC was tested at 13.3 Mb/s, has a 1.2 μs latency, and consumes 185 mW on a single 3.3-V power supply, resulting in an energy consumption of 13.9 nJ per decoded bit, thus reducing the energy consumption by 70% relative to existing digital turbo decoders. The core area is 1131.2×1257.9 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The addition of swinging buffers could triple the speed and reduce the latency with minimal increase in power consumption by overlapping storage and decoding phases. Mismatch simulations show that the circuits will be viable for decoder lengths up to a few hundred information bits.