Designer-controlled generation of parallel and flexible heterogeneous MPSoC specification

Abstract

Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potential available through MPSoC architectures depends heavily on the effectiveness of this programming. Existing automatic parallelizing techniques, though effective on shared memory architectures, are insufficient for MPSoCs, which are typically characterized by heterogeneous processing elements and memory architectures. The lack of effective automatic techniques requires designers to manually partition the code and the data structures in the reference application to generate a parallel and flexible specification. Manual creation of this model is time consuming and error prone.