High-voltage planar devices using field plate and semi-resistive layers

Abstract

An improved high-voltage technique based on the use of a field plate combined with semiresistive layers (SIPOS) on oxide is proposed. The field plate and SIPOS (semi-insulating polycrystalline silicon) are shown to have complementary functions. Junction curvature electric field effects are reduced by the presence of the field plate. The silicon surface potential is linearized by a primary SIPOS layer on oxide, thereby reducing the peak electric field at the edge of the field plate. A second high-resistivity SIPOS layer provides an excellent passivation, and also prevents the dielectric breakdown of the underlayer SIPOS film. Moreover, the savings in chip area is about 20% compared to the standard mesa termination. The global yield is 94% for the SIPOS planar transistors and 86% for equivalent devices in mesa technology. The complete fabrication, design, electrical characteristics, and reliability of high-voltage planar transistors are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>