Frequency multiplier using waveguide-based spatial power-combining architecture

Abstract

In this paper, an architecture of a frequency multiplier is proposed and demonstrated with emphasis on the development of a 12-24-GHz frequency doubler based on a waveguide spatial power-combining technique. This frequency doubler is designed by spatially combining four monolithic-microwave integrated-circuit multiplier chips operating from 11-13 to 22-26 GHz. The output power obtained is 22.6 dBm for 21-dBm input power, which corresponds to a combining efficiency of 74%. The suppression of unwanted harmonics has been achieved by inherent properties of the architecture. The suppression of the first harmonic obtained in this paper is more than 65 dB, whereas at least 25 dB is expected for the third harmonic. This new design technique optimizes the conversion efficiency and also allows a significant loss reduction, as the usually needed output filters are no longer required.