Analysis and reduction of signal readout circuitry temporal noise in CMOS image sensors for low-light levels

TLDR

Low‑frequency and thermal noise are significant contributors to CMOS image sensor performance. The paper presents an analytical noise analysis of correlated double sampling readout circuits in CMOS active‑pixel image sensors. The analysis models reset noise, floating‑diffusion capacitance effects, and charge‑to‑voltage conversion gain, emphasizes output variance over noise spectrum, and is validated by test circuits fabricated in a standard 0.7 µm CMOS process. The analysis enables calculation of output RMS noise versus MOS transistor dimensions using SPICE simulations, and the theoretical predictions agree with experimental measurements.

Abstract

In this paper, analytical noise analysis of correlated double sampling (CDS) readout circuits used in CMOS active pixel image sensors is presented. Both low-frequency noise and thermal noise are considered. The results allow the computation of the output RMS noise versus MOS transistor dimensions with the help of SPICE-based circuit simulators. The reset noise, the influence of floating diffusion capacitance on output noise and the detector charge-to-voltage conversion gain are also considered. Test circuits were fabricated using a standard 0.7 /spl mu/m CMOS process to validate the results. The analytical noise analysis in this paper emphasizes the computation of the output variance, and not the output noise spectrum, as more suitable to CDS operation. The theoretical results are compared with the experimental data.