Practical aspects of high speed switched-capacitor decimation filter implementation

Abstract

A new approach for monolithic CMOS implementation of the low-pass filter function in analog front-ends for receivers in high speed data communications applications is presented. The approach is based on switched-capacitor transversal filter structures employing parallelism and pipelining to increase throughput. Architectures appropriate for filters with both short and long impulse responses are presented along with necessary hardware requirements. Limitations and the effect of non-idealities on the proposed approach are also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>