Rail-to-rail multiple-input min/max circuit

Abstract

The author presents a multiple-input min/max circuit technique that reduces the errors associated with previous analog implementations by combining a common-source voltage-mode configuration with a current-mode "winner takes all" circuit. The overall architecture exhibits linear complexity with the number of inputs. Both minimum and maximum two-input prototypes have been designed and built in a 2-/spl mu/m CMOS process. The active area for each circuit is 650/spl times/100 /spl mu/m/sup 2/, and the total power dissipation is 0.8 mW from a single 5-V supply. Experimental results confirm rail-to-rail operation and sharp transition regions.