A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications

Abstract

This paper presents the design of a 64-PE folded-torus intra-chip communication fabric used to provide guaranteed throughput in terms of dead- and live-lock free and in-order data delivery, which is suitable for NoC-based real-time processing applications. A test chip using the proposed intra-chip communication fabric designed to integrate 64 RISC-based processing elements is fabricated in 1P6M 0.13 mum CMOS technology with 23 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area. At room temperature, the measured peak power (all PE-tiles activated) of the test chip is 200 mW @ 128 MHz at 1.2 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cc</sub> . The intra-chip network consuming 9. 4% the chip area and 18% of the total chip power can provide a maximum bisection bandwidth of 44.6 Gb/s with an approximate energy per transported bit of 0.14 pJ/bit/hop.