The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-Core Microprocessors

Abstract

We present a new closed-form compact model for conductor resistivity considering size effects, line-edge roughness and CMP dishing. Using this model, Monte Carlo simulations quantify the impact of interconnect variations on maximum critical path delay distributions for future technologies. Results indicate LER amplitudes start to become a substantial percentage of the nominal effective line-width dimension (2016 to 2020), leading to an increase in the conductor resistivity. Moreover, multi-core systems exhibit better tolerance to interconnect variations due to their short-wire architecture - as much as a 35% reduction for the maximum critical path delay mean degradation and standard deviation is observed for the year 2020 with a 14 nm half-pitch.