Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains

Abstract

This paper presents an approach to the automatic mapping of arbitrary combinational circuits to the arithmetic carry-chain structures widely available in modern FPGAs. This capability is highly valuable as it enables the utilization of these fast special-purpose structures for general-purpose logic. The described approach is both automatic and generally applicable to all carry-chain architectures designed for binary addition. It, thus, lifts severe constraints left by previous works. It helps to reduce the pressure on the general-purpose routing resources and accelerates critical logic paths. The proposed mapping is further shown to enhance the logic capability of a logic block containing a k-input lookup table (k-LUT) to implement many (k+1)-input functions on common FPGA architectures. This, in particular, also applies to all logic functions with a non-inverting path as introduced by Anderson and Wang. This makes their envisioned gains in logic density achievable even on current devices without requiring their architectural extension. The benefits of the carry-chain mapping are experimentally evaluated on the basis of combinational MCNC benchmarks. It is shown how carry chains can be recovered within a functional standard mapping and that a device mapping aware of carry chains achieves a reduction of the combinational delay of about a 20 percent.