Impact analysis of process variability on clock skew

Abstract

This paper presents a methodology for the statistical analysis of clock tree structures. It allows to accurately predict and analyze the impact of process variation on clock skew. The methodology is divided in three phases. The first phase is a topological analysis used to screen non-critical network configurations, which does not require computationally expensive steps such as parasitic extraction and circuit-level simulation. The second phase is a detailed nominal skew computation based on accurate 3D extraction, performed on a small set of configurations identified as critical by the topological analysis. The third phase is a variational analysis of the impact of process variations and design parameters on the clock skew, that might induce timing margin violations. This methodology has been implemented for scan chain analysis and validated on an industrial strength test case.