IEEE Journal of Solid-State Circuits · 1981 · 41 citations · 3 references
Electrical EngineeringEngineeringVlsi DesignTimes/31 Bit RomTtl BuffersData Converter5-Bit Building BlockMixed-signal Integrated CircuitComputer EngineeringComputer ArchitectureDigital Circuit DesignPower ElectronicsDc LinearityMicroelectronicsAnalog-to-digital Converter
Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.
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