Publication | Closed Access
A 1.8 V 36 mW DSP for the half-rate speech codec
10
Citations
3
References
2002
Year
Unknown Venue
Dual Datapath ArchitectureEngineeringAnalog DesignHalf-rate Speech CodecLow-power 16-Bit DspMw DspSpeech RecognitionSpeech CodingAudio Signal ProcessingV 36NoiseAnalog-to-digital ConverterHealth SciencesData ConverterComputer EngineeringDistant Speech RecognitionPower ConsumptionSignal ProcessingDigital AudioSpeech Processing
A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V.
| Year | Citations | |
|---|---|---|
Page 1
Page 1