AES Crypto Chip Utilizing High-Speed Parallel Pipelined Architecture

Abstract

In November 2001, the National Institute of Standards and Technology (NIST) of the USA chose the Rijndael algorithm as the suitable Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES) algorithm. Since then, many hardware implementations have been proposed in literature. We present a hardware-efficient design increasing throughput for the AES algorithm using a high-speed parallel pipelined architecture. By using an efficient inter-round and intra-round pipeline design, our implementation achieves a high throughput of 29.77 Gbit/s in encryption whereas the highest throughput reported in the literature is 21.54 Gbit/s.