2015 · 59 citations · 37 references
ComputingComputer EngineeringComputer ScienceComputer SecurityNetwork SecuritySystem-on-chip DesignDenial-of-service AttacksEmbedded SecurityEmbedded System SecurityHardware TrojansMicroarchitectural SecurityNetwork-on-chip DesignCovert ResistanceCross-layer DesignCross-layer Latency AnalysisDenial Of Service Attack MitigationNetwork LatencyRuntime Anomaly DetectionRuntime Vulnerability DetectionSecurity In Network-on-chip
In this paper, we propose a covert threat model for MPSoCs designed using 3rd party Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on-chip resources, thereby causing large performance bottlenecks for the software running on the MPSoC platform. We then propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. For the proposed technique, our comprehensive cross-layer analysis indicates modest overheads of 12.73% in area, 9.844% in power and 5.4% in terms of network latency.
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