SiC Integrated MOSFETs

Abstract

A new design and processing concepts have been applied to develop practical SiC trench MOSFETs for high power applications. The designed trench MOSFET has a MOS structure consisting of epitaxially grown n-type SiC trench sidewall layers. The current flows via an accumulation mode through the channel defined in the epitaxially grown SiC sidewall layer. The channel is depleted by the built-in fields of the p-type SiC base layer and the p-poly-Si gate, that control the channel conditions. The simulation based investigations revealed that the formed channel can withstand up to the avalanche breakdown condition. The structure of the n-type SiC trench sidewall epi-layer has been optimized to realize the blocking voltage of more than 1000 V for SiC MOSFETs with low on-state resistance. Moreover, our designed structure can address most of the open issues related to the MOS interface, viz., high surface state density, low channel mobility and high electric field at the trench base of the MOS structure. We have fabricated the first 2 mm square large size 6H-SiC trench MOSFET chip, in which 2380 hexagonal structural microcells of 23 μm pitch were integrated. The fabricated 6H-SiC trench MOSFET on (0001-) C-face wafers feature the on-state resistance as low as 23.84 m Ω cm2 with blocking voltage of more than 450 V.