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The architecture of delta sigma analog-to-digital converters using a voltage-controlled oscillator as a multibit quantizer
107
Citations
5
References
1999
Year
Analog System EngineeringMultibit QuantizerData Converterδ-σ AdcVoltage-controlled OscillatorAnalog DesignMixed-signal Integrated CircuitDigital Circuit DesignLow Voltage OperationDelta-sigma Analog-to-digital ConverterAnalog-to-digital Converter
The brief proposes a new architecture for an oversampling delta‑sigma ADC that uses a voltage‑controlled oscillator (VCO) as the core component. The design couples the VCO to a pulse counter to form a high‑speed, first‑order noise‑shaping quantizer, tunes the VCO frequency to (2^bq‑2)f_os < f_vm < (2^bq‑1)f_os to realize a multibit (bq‑bit) quantizer, and evaluates its performance via functional simulation. Simulation results show the converter achieves 59‑dB SNR at 5‑MHz bandwidth with f_os = 400 MHz even using a 1‑bit quantizer, and the multibit VCO‑based quantizer further improves SNR and bandwidth, making it suitable for deep‑sub‑µm CMOS, wide‑band video and wireless applications, and low‑voltage SoC multimedia solutions.
This brief proposes a new- architecture for the oversampling delta-sigma analog-to-digital converter (Δ-Σ ADC) utilizing a voltage controlled oscillator (VCO). The VCO, associated with a pulse counter, works as a high-speed quantizer. This VCO quantizer also has the function of first-order noise shaping because the phase of the output pulse is an integrated quantity of the input voltage. If the maximum VCO frequency (fvm) is designed in the range of (2/sup bq/-2)fos < fvm < (2/sup bq/-1) fos and a bq-bit counter is used, a multibit (bq-bit) quantizer can be realized, where fos is the oversampling frequency. The performance of the proposed converter is evaluated using a functional simulation. A 59-dB SNR at a 5-MHz bandwidth is obtained with fos = 400 MHz, even in the case of a 1-bit quantizer. The multibit quantizer using a high frequency VCO significantly improves an SNR and signal bandwidth. This architecture is highly suitable for implementation with deep sub-μm CMOS devices, which can attain improved switching speeds and reduce power dissipation during low voltage operation. It provides wideband oversampling ADC for video and wireless signals and a low voltage system-on-a-chip solution for multimedia applications.
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