Asia Pacific Conference on Circuits and Systems · 2003 · 50 citations · 12 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysSystem-on-chip DesignDigital Image ProcessingDigital Signal ProcessingFpga ArchitectureImage ProcessingMemory Hierarchy DesignSignal ProcessingBuffer SpacesComplexityDigital Signal Processing BlocksDiscrete Wavelet TransformLine-based Data StructuresPyramid ArchitectureWavelet AnalysisWavelet Transform
In this paper, by using line-based methods, a generic RAM-based architecture is proposed to construct the corresponding two-dimensional architectures efficiently for any given hardware architecture of one-dimensional wavelet filters, including conventional convolution-based and advanced lifting-based architectures. The categories of line buffer and the strategy to optimize the size of internal memory are also described. For multi-level two-dimensional discrete wavelet transforms, the recursive pyramid algorithm is adopted to turn our proposed architecture into another efficient architecture. According to the comparison results, the proposed architecture outperforms previous arts in the aspects of memory size, control complexity, and flexibility.
12