IEEE Transactions on Signal Processing · 1995 · 219 citations · 14 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysParallel ComputingDigital Image ProcessingDigital Signal ProcessingField-programmable Gate Array ArchitectureImage ProcessingParallel ArchitecturesSignal ProcessingContinuous Wavelet TransformDiscrete Wavelet TransformSimd ArchitecturesSimd ParallelismStorageSystolic Array DesignSystolic ArraysWavelet Transform
This paper presents a wide range of algorithms and architectures for computing the 1D and 2D discrete wavelet transform (DWT) and the 1D and 2D continuous wavelet transform (CWT). The algorithms and architectures presented are independent of the size and nature of the wavelet function. New on-line algorithms are proposed for the DWT and the CWT that require significantly small storage. The proposed systolic array and the parallel filter architectures implement these on-line algorithms and are optimal both with respect to area and time (under the word-serial model). Moreover, these architectures are very regular and support single chip implementations in VLSI. The proposed SIMD architectures implement the existing pyramid and a'trous algorithms and are optimal with respect to time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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