EngineeringComputer EngineeringComputer ScienceComputer ArchitectureFault-tolerant ComputingFault-tolerant SystemsFault Tolerance In Parallel SystemsGraphics Processing Unit ArchitectureHardware Fault ToleranceParallel ArchitecturesParallel Computer ArchitectureParallel Computing SystemsEngineering RequirementsFault-tolerant ArchitectureFault-tolerant Processor DesignParallel Computing Architectures
The new decade (1990-2000) heralds the age of very powerful compute-, graphics- and information-servers, based on Massively Parallel Processors (mppS), capable of TOPS (Tera Operations-Per-Second) performance in networked scientific, engineering, knowledge-base and artificial intelligence applications. This paper describes a WSI associative string processor (WASP) in CMOS fault-tolerant WSI MPP architecture which satisfies both the architectural and engineering requirements outlined and, thereby, offers a step-function improvement in cost-effectiveness compared with first-generation MPPs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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ASP: a cost-effective parallel microcomputer
R.M. Lea · IEEE Micro · 1988 · 74 citations
WASP: a WSI associative string processor
I.P. Jalowiecki, K.D. Warrent, R.M. Lea · 2003 · 18 citations
Performance of the ASP on the DARPA architecture benchmark
A. Krikelis, R.M. Lea · 2003 · 10 citations