IEEE Journal of Solid-State Circuits · 1995 · 68 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignSystem-on-chip DesignAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsMixed-signal Integrated Circuit DesignMixed-signal IntegrationAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersDigital-to-analog ConvertersGlitch Power ReductionSettlingSettling Time
A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 /spl mu/m single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV/spl middot/s and the settling time within /spl plusmn/0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm/spl times/1.2 mm (1.75 mm/spl times/0.7 mm for the DAC portion).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
6
An 80-MHz 8-bit CMOS D/A converter
T. Miki, Yohei Nakamura, M. Nakaya et al. · IEEE Journal of Solid-State Circuits · 1986 · 240 citations