A 12-bit 500-ns subranging ADC

M. Kolluri

IEEE Journal of Solid-State Circuits · 1989 · 15 citations · 5 references

Concepts

Abstract

A subranging 12-b ADC (analog/digital converter) with analog and digital correction has been developed in a high-speed bipolar process. A conversion is performed in four stages. The settling requirement of the subtraction digital/analog converters is postponed until the final stage, resulting in a conversion time of 500 ns. The use of Ti-W fuse-link based trimming permits the critical circuit components to be adjusted at the wafer level with only a few pads. The circuit has been implemented in a die area of 25 mm/sup 2/ and dissipates 650 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

References

5