IEEE Journal of Solid-State Circuits · 1988 · 16 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsComputer ArchitectureMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsMixed-signal Integrated Circuit DesignMixed-signal IntegrationA-d ConversionAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital Converter IntegrationAnalog-to-digital ConvertersDigital Signal Processing Block ArchitecturePrototype Performance Evaluation
A microprocessor-compatible, 14-bit, 10- mu s subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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