An energy-efficient leakage-tolerant dynamic circuit technique

Abstract

Technology scaling reduces device threshold voltages to mitigate speed loss due to scaled supply voltages. This, however, exponentially increases leakage power and adversely affects circuit reliability. In this paper, we investigate the performance degradation in high-leakage digital circuits. It is shown that deep submicron CMOS technologies lead to 60%-70% degradation in noise-immunity due to leakage. Dual-V/sub t/ domino designs mitigate the noise-immunity degradation to 30%-40% but inevitably lead to a loss of 20%-30% in circuit speed. To achieve a better noise-immunity vs. performance trade-off, a new dynamic circuit technique-the boosted-source (BS) technique is proposed. Simulation results of wide fan-in gates designed in the Predictive Berkeley BSIM3v3 0.13 /spl mu/m technology demonstrate 1.6X-3X improvement in noise-immunity at the expense of marginal energy overhead but no loss in delay, as compared with the existing circuit techniques.