Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

TLDR

The paper proposes a method to predict memory chip yield from cell‑failure probability and a statistical design methodology for SRAM cells and organization using these models. The strategy statistically sizes SRAM transistors and optimizes redundant columns to reduce failure probability while respecting area and leakage constraints. The authors modeled access‑time, read/write, and hold failure probabilities of SRAM cells due to process variations and show that the method can be applied early in the design cycle to improve memory yield at the nanoscale.

Abstract

In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is proposed using the failure-probability and the yield-prediction models. The developed design strategy statistically sizes different transistors of the SRAM cell and optimizes the number of redundant columns to be used in the SRAM array, to minimize the failure probability of a memory chip under area and leakage constraints. The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime.